LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
| dc.citation.epage | 1328 | en_US |
| dc.citation.issue | 9 | en_US |
| dc.citation.spage | 1324 | en_US |
| dc.citation.volume | 26 | en_US |
| dc.citation.woscount | 10 | |
| dc.contributor.author | WU, CY | en_US |
| dc.contributor.author | CHENG, KH | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:05:10Z | |
| dc.date.available | 2014-12-08T15:05:10Z | |
| dc.date.issued | 1991-09-01 | en_US |
| dc.description.abstract | A new CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate, and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results have verified the high speed and race-free performance of the proposed LCDL. | en_US |
| dc.identifier.doi | 10.1109/4.84952 | en_US |
| dc.identifier.issn | 0018-9200 | en_US |
| dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/4.84952 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3692 | |
| dc.identifier.wosnumber | WOS:A1991GC00300019 | |
| dc.language.iso | en_US | en_US |
| dc.title | LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI | en_US |
| dc.type | Note | en_US |