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Threshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistor

dc.citation.epage245en_US
dc.citation.issue3en_US
dc.citation.spage243en_US
dc.citation.volume30en_US
dc.citation.woscount7
dc.contributor.authorHsu, Hsing-Huien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorChan, Lengen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department奈米中心zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentNano Facility Centeren_US
dc.date.accessioned2014-12-08T15:09:52Z
dc.date.available2014-12-08T15:09:52Z
dc.date.issued2009-03-01en_US
dc.description.abstractIn this letter, the fluctuation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) with independently controlled double-gate configuration were studied. The defects existing in the NW channels are identified as one of the major sources for the fluctuation. The passivation of these defects by plasma treatment is shown to be effective for reducing the fluctuation. We have also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the switching behavior of the device, an optimum bias for the other gate can be found for minimizing the fluctuation.en_US
dc.identifier.doi10.1109/LED.2008.2011568en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2008.2011568en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/7555
dc.identifier.wosnumberWOS:000263920400014
dc.language.isoen_USen_US
dc.subjectDouble gateen_US
dc.subjectfluctuationen_US
dc.subjectnanowire (NW)en_US
dc.subjectpolycrystalline silicon (poly-Si)en_US
dc.titleThreshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistoren_US
dc.typeArticleen_US

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