IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
| dc.citation.epage | 23 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 14 | en_US |
| dc.citation.volume | 12 | en_US |
| dc.citation.woscount | 8 | |
| dc.contributor.author | LIANG, HC | en_US |
| dc.contributor.author | LEE, CL | en_US |
| dc.contributor.author | CHEN, JE | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:03:13Z | |
| dc.date.available | 2014-12-08T15:03:13Z | |
| dc.date.issued | 1995-09-01 | en_US |
| dc.description.abstract | This article proposes an efficient method to identify untestable faults in sequential circuits. It uses a controllability calculation and symbolic simulation procedure that propagates the characteristics of unknown initial flip-flop states throughout the circuit. Identifying flip-flops that cannot be initialized and circuit lines that cannot be justified to definite values, this process classifies and identifies four types of untestable faults. Experimental results show that it improves the efficiency of a test generation system. | en_US |
| dc.identifier.doi | 10.1109/MDT.1995.466367 | en_US |
| dc.identifier.issn | 0740-7475 | en_US |
| dc.identifier.journal | IEEE DESIGN & TEST OF COMPUTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/MDT.1995.466367 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/1770 | |
| dc.identifier.wosnumber | WOS:A1995RP81200006 | |
| dc.language.iso | en_US | en_US |
| dc.title | IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS | en_US |
| dc.type | Article | en_US |