Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer
| dc.citation.epage | en_US | |
| dc.citation.issue | 1 | en_US |
| dc.citation.volume | 53 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Lee, Ko-Hui | en_US |
| dc.contributor.author | Lin, Horng-Chih | en_US |
| dc.contributor.author | Huang, Tiao-Yuan | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:35:08Z | |
| dc.date.available | 2014-12-08T15:35:08Z | |
| dc.date.issued | 2014-01-01 | en_US |
| dc.description.abstract | Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics. (C) 2014 The Japan Society of Applied Physics | en_US |
| dc.identifier.doi | 10.7567/JJAP.53.014001 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.7567/JJAP.53.014001 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/23850 | |
| dc.identifier.wosnumber | WOS:000331412300027 | |
| dc.language.iso | en_US | en_US |
| dc.title | Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer | en_US |
| dc.type | Article | en_US |