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Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation

dc.citation.epage+en_US
dc.citation.spage405en_US
dc.citation.woscount19en_US
dc.contributor.authorWu, Woei-Chemgen_US
dc.contributor.authorLai, Chao-Sungen_US
dc.contributor.authorLee, Shih-Chingen_US
dc.contributor.authorMa, Ming-Wenen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorWang, Jer-Chyien_US
dc.contributor.authorHsu, Chih-Weien_US
dc.contributor.authorChou, Pai-Chien_US
dc.contributor.authorChen, Jian-Haoen_US
dc.contributor.authorKao, Kuo-Hsingen_US
dc.contributor.authorLo, Wen-Chengen_US
dc.contributor.authorLu, Tsung-Yien_US
dc.contributor.authorTay, Li-Linen_US
dc.contributor.authorRowell, Nelsonen_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.date.accessioned2017-04-21T06:48:53Z
dc.date.available2017-04-21T06:48:53Z
dc.date.issued2008en_US
dc.description.abstractIn this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.en_US
dc.identifier.isbn978-1-4244-2377-4en_US
dc.identifier.journalIEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGESTen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/135086
dc.identifier.wosnumberWOS:000265829300092en_US
dc.language.isoen_USen_US
dc.titleFluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivationen_US
dc.typeProceedings Paperen_US

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