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Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions

dc.citation.epage683en_US
dc.citation.issue6en_US
dc.citation.spage681en_US
dc.citation.volume30en_US
dc.citation.woscount2
dc.contributor.authorLin, S. H.en_US
dc.contributor.authorCheng, C. H.en_US
dc.contributor.authorChen, W. B.en_US
dc.contributor.authorYeh, F. S.en_US
dc.contributor.authorChin, Alberten_US
dc.contributor.department機械工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Mechanical Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:09:23Z
dc.date.available2014-12-08T15:09:23Z
dc.date.issued2009-06-01en_US
dc.description.abstractWe demonstrate a low threshold voltage (V,) of -0.17 V and good hole mobility (54 cm(2)/V (.) s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.en_US
dc.identifier.doi10.1109/LED.2009.2020307en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2009.2020307en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/7162
dc.identifier.wosnumberWOS:000266409200032
dc.language.isoen_USen_US
dc.subjectLaTiOen_US
dc.subjectlow V(t)en_US
dc.subjectsolid-phase diffusion (SPD)en_US
dc.titleLow-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctionsen_US
dc.typeArticleen_US

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