A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

Abstract

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q(inv) and effective mobility mu(eff) has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C(of) and C(f(poly-end)), respectively. Both categories of parasitic capacitance lead to overestimated Q(inv) and underestimated mu(eff). The increase in effective channel width W(eff) due to Delta W from shallow trench isolation (STI) top-corner rounding may compensate mu(eff) degradation due to STI stress. The tradeoff between mu(eff) and W(eff) determines the impact of width scaling on I(DS) and G(m). A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of mu(eff) in multifinger MOSFETs with various layouts and narrow widths down to 0.125 mu m.