Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique

Abstract

Crosstalk between bit lines leads to read-1 failure in a high-speed via-programmable read only memory (ROM) and limits the coverage of applicable code patterns. Due to the fluctuations in bit-line intrinsic and coupling capacitances, the amount of noise coupled to a selected bit line may vary, resulting in the reduction of sensing margin. In this paper, we propose a dynamic bit-line shielding (DBS) technique, suitable to be implemented in compliable ROM, to eliminate the crosstalk-induced read failure and to achieve full code coverage. Experiments of the 256Kb instances with and without the DBS circuit were undertaken using 0.25 mu m and 0.18 mu m standard CMOS processes. The test results demonstrate the read-1 failures and confirm that the DBS technique can remove them successfully, allowing the ROM to operate under a wide range of supply voltage.