Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels

Abstract

The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved ON-current per unit width and better control over the short channel effects. The major conduction mechanism of the OFF-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.