Planar junctionless poly-Si thin-film transistors with single gate and double gate
| dc.citation.epage | en_US | |
| dc.citation.issue | 6 | en_US |
| dc.citation.volume | 53 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Chou, Chia-Hsin | en_US |
| dc.contributor.author | Lee, I-Che | en_US |
| dc.contributor.author | Lei, Dai-Che | en_US |
| dc.contributor.author | Cheng, Huang-Chung | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:36:19Z | |
| dc.date.available | 2014-12-08T15:36:19Z | |
| dc.date.issued | 2014-06-01 | en_US |
| dc.description.abstract | In this letter, single-and double-gate (SG and DG) planar junctionless (JL) thin-film transistors fabricated via a simple process with an in situ-doped active layer is discussed. The DG structure demonstrated a superior subthreshold swing of 160mV/dec and a lower off-current of 1.3 x 10(-13)A than those of 329mV/dec and 2.1 x 10(-12)A for the SG structure, respectively. It contributes to the enhancement of the gate controllability and ultrathin channel. Consequently, the simple fabrication process of the DG JL device is suitable for future application on system-on-panel and three-dimensional integrated circuits. (C) 2014 The Japan Society of Applied Physics | en_US |
| dc.identifier.doi | 10.7567/JJAP.53.06JE07 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.7567/JJAP.53.06JE07 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/24664 | |
| dc.identifier.wosnumber | WOS:000338439500026 | |
| dc.language.iso | en_US | en_US |
| dc.title | Planar junctionless poly-Si thin-film transistors with single gate and double gate | en_US |
| dc.type | Article | en_US |