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Novel Two-Bit-per-Cell Resistive-Switching Memory for Low-Cost Embedded Applications

dc.citation.epage1664en_US
dc.citation.issue12en_US
dc.citation.spage1662en_US
dc.citation.volume32en_US
dc.citation.woscount3
dc.contributor.authorWu, Shih-Chiehen_US
dc.contributor.authorLo, Chiehen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:21:00Z
dc.date.available2014-12-08T15:21:00Z
dc.date.issued2011-12-01en_US
dc.description.abstractA novel two-bit-per-cell embedded nonvolatile memory (NVM) device requiring no additional mask and process modification in a logic technology has been proposed using a low-temperature poly-Si thin-film transistor with a HfO(2)/Ni gate stack. The feature of two-bit-per-cell is realized by independent localized resistive switching (RS) at the drain and source bits, respectively, and enables increased bit density over the present single-poly NVM for low-cost embedded applications. Furthermore, minimal degradation of the transistor characteristics after RS allows interchangeable logic/memory operations in an identical device.en_US
dc.identifier.doi10.1109/LED.2011.2167711en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2011.2167711en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/14921
dc.identifier.wosnumberWOS:000297352500005
dc.language.isoen_USen_US
dc.subjectEmbedded nonvolatile memory (NVM)en_US
dc.subjectresistive switching (RS)en_US
dc.subjectresistive-switching random access memory (RRAM)en_US
dc.subjecttwo-bit-per-cellen_US
dc.titleNovel Two-Bit-per-Cell Resistive-Switching Memory for Low-Cost Embedded Applicationsen_US
dc.typeArticleen_US

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