A millisecond-anneal-assisted selective fully silicided (FUSI) gate process

Abstract

We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (NISA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for PMOSFETs with the feature size down to 30 run. A 20% improvement in FUSI-gated PMOSFET I-on-I-off is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.