A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's

Abstract

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N-it) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N-it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N-it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.