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Investigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance model

dc.citation.epage1873en_US
dc.citation.issue4Ben_US
dc.citation.spage1870en_US
dc.citation.volume46en_US
dc.contributor.authorLee, Weien_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorSu, Ke-Weien_US
dc.contributor.authorChiang, Chung-Shien_US
dc.contributor.authorLiu, Sallyen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:06:23Z
dc.date.available2014-12-08T15:06:23Z
dc.date.issued2007-04-01en_US
dc.description.abstractThis paper presents an inversion capacitance-voltage (C-V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (R-ii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with V-Gs and L, our R-ii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.en_US
dc.identifier.doi10.1143/JJAP.46.1870en_US
dc.identifier.issn0021-4922en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERSen_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.46.1870en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/4948
dc.identifier.wosnumberWOS:000247050200009
dc.language.isoen_USen_US
dc.subjectMOSFETen_US
dc.subjectMOS capacitanceen_US
dc.subjectC-Ven_US
dc.subjectultrathin gate oxide and intrinsic input resistanceen_US
dc.titleInvestigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance modelen_US
dc.typeArticle; Proceedings Paperen_US

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