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Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations

dc.citation.epageen_US
dc.citation.issue9en_US
dc.citation.volume21en_US
dc.citation.woscount7
dc.contributor.authorLi, Yimingen_US
dc.contributor.authorHwang, Chih-Hongen_US
dc.contributor.authorHan, Ming-Hungen_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.date.accessioned2014-12-08T15:07:15Z
dc.date.available2014-12-08T15:07:15Z
dc.date.issued2010-03-05en_US
dc.description.abstractHigh-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold voltage, gate capacitance and cutoff frequency have been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, its impact is reduced in AC characteristics due to the screening effect of the inversion layer. Additionally, the channel discrete dopant may enhance the electric field and therefore make the averaged cutoff frequency of fluctuated devices larger than the nominal value of cutoff frequency.en_US
dc.identifier.doi10.1088/0957-4484/21/9/095203en_US
dc.identifier.issn0957-4484en_US
dc.identifier.journalNANOTECHNOLOGYen_US
dc.identifier.urihttp://dx.doi.org/10.1088/0957-4484/21/9/095203en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/5730
dc.identifier.wosnumberWOS:000274360300005
dc.language.isoen_USen_US
dc.titleSimulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuationsen_US
dc.typeArticleen_US

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