Fully static processor optimal assignment of data-flow graphs
| dc.citation.epage | 148 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 146 | en_US |
| dc.citation.volume | 4 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Ho, YC | en_US |
| dc.contributor.author | Tsay, JC | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:01:49Z | |
| dc.date.available | 2014-12-08T15:01:49Z | |
| dc.date.issued | 1997-05-01 | en_US |
| dc.description.abstract | The data-flow graph (DFG) is an important graph-theoretic model for multiprocessor implementation of real-time digital signal processing (DSP) algorithms. Given a time schedule for a DFG,, we consider the problem of the processor-optimal assignment for a fully static schedule. Previously, the solution of this problem was found by solving an integer programming problem. In this letter, we propose a linear programming approach to solving the problem. | en_US |
| dc.identifier.doi | 10.1109/97.575560 | en_US |
| dc.identifier.issn | 1070-9908 | en_US |
| dc.identifier.journal | IEEE SIGNAL PROCESSING LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/97.575560 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/583 | |
| dc.identifier.wosnumber | WOS:A1997WW85200010 | |
| dc.language.iso | en_US | en_US |
| dc.title | Fully static processor optimal assignment of data-flow graphs | en_US |
| dc.type | Article | en_US |