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A novel fully CMOS process compatible PREM for SOC applications

dc.citation.epage204en_US
dc.citation.issue3en_US
dc.citation.spage203en_US
dc.citation.volume26en_US
dc.citation.woscount2
dc.contributor.authorYeh, CCen_US
dc.contributor.authorWang, THen_US
dc.contributor.authorTsai, WJen_US
dc.contributor.authorLu, TCen_US
dc.contributor.authorLiao, YYen_US
dc.contributor.authorZous, NKen_US
dc.contributor.authorChin, CYen_US
dc.contributor.authorChen, YRen_US
dc.contributor.authorChen, MSen_US
dc.contributor.authorTing, WCen_US
dc.contributor.authorLu, CYen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:19:37Z
dc.date.available2014-12-08T15:19:37Z
dc.date.issued2005-03-01en_US
dc.description.abstractA novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.en_US
dc.identifier.doi10.1109/LED.2005.843221en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2005.843221en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/13959
dc.identifier.wosnumberWOS:000227262500026
dc.language.isoen_USen_US
dc.subjecteraselessen_US
dc.subjectmultilevel cell (MLC)en_US
dc.subjectnonvolatileen_US
dc.subjectmultitime programming (MTP)en_US
dc.subjectprogressive breakdownen_US
dc.subjectprogrammable resistor with eraseless memory (PREM)en_US
dc.subjectsystem on chip (SOC)en_US
dc.titleA novel fully CMOS process compatible PREM for SOC applicationsen_US
dc.typeArticleen_US

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