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Impact of Uniaxial Strain on Low-Frequency Noise in Nanoscale PMOSFETs

dc.citation.epage674en_US
dc.citation.issue6en_US
dc.citation.spage672en_US
dc.citation.volume30en_US
dc.citation.woscount11
dc.contributor.authorKuo, Jack J. -Y.en_US
dc.contributor.authorChen, William P. -N.en_US
dc.contributor.authorSu, Pinen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:09:23Z
dc.date.available2014-12-08T15:09:23Z
dc.date.issued2009-06-01en_US
dc.description.abstractThis letter investigates the low-frequency noise characteristics and reports a new mechanism for uniaxial strained PMOSFETs. Through a comparison of the input-referred noise and the trap density of the gate dielectric/semiconductor interface between co-processed strained and unstrained devices, it is found that the tunneling attenuation length for channel carriers penetrating into the gate dielectric is reduced by uniaxial strain. The reduced tunneling attenuation length may result in smaller input-referred noise, which represents an intrinsic advantage of low-frequency noise performance stemming from process-induced strain.en_US
dc.identifier.doi10.1109/LED.2009.2020069en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2009.2020069en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/7161
dc.identifier.wosnumberWOS:000266409200029
dc.language.isoen_USen_US
dc.subjectInterface stateen_US
dc.subjectlow-frequency noiseen_US
dc.subjectprocess-induced strainen_US
dc.subjecttrap densityen_US
dc.subjecttunneling attenuation lengthen_US
dc.subjectuniaxial strained PMOSFETen_US
dc.titleImpact of Uniaxial Strain on Low-Frequency Noise in Nanoscale PMOSFETsen_US
dc.typeArticleen_US

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