A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array
| dc.citation.epage | 0 | en_US |
| dc.citation.spage | 0 | en_US |
| dc.citation.volume | 7 | en_US |
| dc.citation.woscount | 6 | en_US |
| dc.contributor.author | Zackriya, Mohammed, V | en_US |
| dc.contributor.author | Kittur, Harish M. | en_US |
| dc.contributor.author | Chin, Albert | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2019-04-03T06:36:44Z | |
| dc.date.available | 2019-04-03T06:36:44Z | |
| dc.date.issued | 2017-02-10 | en_US |
| dc.description.abstract | The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 mu A due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design. | en_US |
| dc.identifier.doi | 10.1038/srep42375 | en_US |
| dc.identifier.issn | 2045-2322 | en_US |
| dc.identifier.journal | SCIENTIFIC REPORTS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1038/srep42375 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/133164 | |
| dc.identifier.wosnumber | WOS:000393789800001 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array | en_US |
| dc.type | Article | en_US |