A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler
| dc.citation.epage | 280 | en_US |
| dc.citation.issue | 12 | en_US |
| dc.citation.spage | 276 | en_US |
| dc.citation.volume | 3 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Shih, Yi-Shing | en_US |
| dc.contributor.author | Tarng, Jenn-Hwan | en_US |
| dc.contributor.department | 電信工程研究所 | zh_TW |
| dc.contributor.department | Institute of Communications Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:16:21Z | |
| dc.date.available | 2014-12-08T15:16:21Z | |
| dc.date.issued | 2006-06-25 | en_US |
| dc.description.abstract | A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dual-modulus prescaler (DMP), implemented in 0.18 mu m CMOS technology, shows a maximum operating frequency of 7.0 GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recently-reported one. | en_US |
| dc.identifier.doi | 10.1587/elex.3.276 | en_US |
| dc.identifier.issn | 1349-2543 | en_US |
| dc.identifier.journal | IEICE ELECTRONICS EXPRESS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1587/elex.3.276 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/12133 | |
| dc.identifier.wosnumber | WOS:000241914100004 | |
| dc.language.iso | en_US | en_US |
| dc.subject | prescaler | en_US |
| dc.subject | high-speed circuits | en_US |
| dc.subject | synchronous counter | en_US |
| dc.title | A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler | en_US |
| dc.type | Article | en_US |