HIGH-SPEED DECODER OF REED-SOLOMON CODES
| dc.citation.epage | 1593 | en_US |
| dc.citation.issue | 11 | en_US |
| dc.citation.spage | 1588 | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.woscount | 9 | |
| dc.contributor.author | WEI, SW | en_US |
| dc.contributor.author | WEI, CH | en_US |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | 電信研究中心 | zh_TW |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.contributor.department | Center for Telecommunications Research | en_US |
| dc.date.accessioned | 2014-12-08T15:04:17Z | |
| dc.date.available | 2014-12-08T15:04:17Z | |
| dc.date.issued | 1993-11-01 | en_US |
| dc.description.abstract | A high speed decoding algorithm using a modified step-by-step method for t-error-correcting Reed-Solomon codes is introduced. Based on this algorithm, a sequential decoder and a vector decoder are then proposed. These two decoders can be constructed by four basic modules: the syndrome calculation module, the comparison module, the decision module, and the shift-control module. These decoders cao be applied for both binary and nonbinary data transmissions working at high data rate. Because of the simplicity in structure and circuit realization, a decoder employing this algorithm can be easily implemented in a monolithic chip by the VLSI technology. | en_US |
| dc.identifier.doi | 10.1109/26.241736 | en_US |
| dc.identifier.issn | 0090-6778 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMMUNICATIONS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/26.241736 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2794 | |
| dc.identifier.wosnumber | WOS:A1993MF63300002 | |
| dc.language.iso | en_US | en_US |
| dc.title | HIGH-SPEED DECODER OF REED-SOLOMON CODES | en_US |
| dc.type | Letter | en_US |