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Failure Analysis of Gate-all-around Nanowire Field Effect Transistor Under TLP Test

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dc.citation.woscount0en_US
dc.contributor.authorZhang, Guoyanen_US
dc.contributor.authorDong, Aihuaen_US
dc.contributor.authorLiu, Nieen_US
dc.contributor.authorTian, Ruien_US
dc.contributor.authorYang, Xuejiaoen_US
dc.contributor.authorLiu, Zhiweien_US
dc.contributor.authorLee, Kohuien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorLiou, Juin J.en_US
dc.contributor.authorWang Yuxinen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.date.accessioned2017-04-21T06:48:54Z
dc.date.available2017-04-21T06:48:54Z
dc.date.issued2014en_US
dc.description.abstractElectrostatic discharge (ESD) characters of Nanowire Field Effect Transistors have been tested and analyzed in detail in this paper. TLP (transmission line pulsing technique) and semiconductor characterization system have been used for experiments. The failure currents and leakage currents of Nanowire Field Effect Transistor are characterized. Also, physical insights and failure model are provided to analyze the failure mechanism.en_US
dc.identifier.isbn978-1-4799-2334-2en_US
dc.identifier.journal2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/135878
dc.identifier.wosnumberWOS:000380453100048en_US
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectTLPen_US
dc.subjectNanowire FETen_US
dc.subjectFailure analysisen_US
dc.titleFailure Analysis of Gate-all-around Nanowire Field Effect Transistor Under TLP Testen_US
dc.typeProceedings Paperen_US

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