Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels
| dc.citation.epage | en_US | |
| dc.citation.issue | 4 | en_US |
| dc.citation.volume | 53 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Tsai, Jung-Ruey | en_US |
| dc.contributor.author | Lee, Ko-Hui | en_US |
| dc.contributor.author | Lin, Horng-Chih | en_US |
| dc.contributor.author | Huang, Tiao-Yuan | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:36:25Z | |
| dc.date.available | 2014-12-08T15:36:25Z | |
| dc.date.issued | 2014-04-01 | en_US |
| dc.description.abstract | A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. (C) 2014 The Japan Society of Applied Physics | en_US |
| dc.identifier.doi | 10.7567/JJAP.53.04ED14 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.7567/JJAP.53.04ED14 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/24751 | |
| dc.identifier.wosnumber | WOS:000338185100049 | |
| dc.language.iso | en_US | en_US |
| dc.title | Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels | en_US |
| dc.type | Article | en_US |