A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-mu m digital CMOS process
| dc.citation.epage | 237 | en_US |
| dc.citation.issue | 1 | en_US |
| dc.citation.spage | 234 | en_US |
| dc.citation.volume | 39 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Chen, WZ | en_US |
| dc.contributor.author | Chang, JX | en_US |
| dc.contributor.author | Hong, YJ | en_US |
| dc.contributor.author | Wong, MT | en_US |
| dc.contributor.author | Kuo, CL | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:39:48Z | |
| dc.date.available | 2014-12-08T15:39:48Z | |
| dc.date.issued | 2004-01-01 | en_US |
| dc.description.abstract | This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-mum digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6 GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 mum x 1600 mum. | en_US |
| dc.identifier.doi | 10.1109/JSSC.2003.820878 | en_US |
| dc.identifier.issn | 0018-9200 | en_US |
| dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2003.820878 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/27191 | |
| dc.identifier.wosnumber | WOS:000188205500024 | |
| dc.language.iso | en_US | en_US |
| dc.subject | dual band | en_US |
| dc.subject | frequency doubler | en_US |
| dc.subject | frequency synthesizer | en_US |
| dc.title | A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-mu m digital CMOS process | en_US |
| dc.type | Article | en_US |