On the prediction of geometry-dependent floating-body effect in SOI MOSFETs
| dc.citation.epage | 1664 | en_US |
| dc.citation.issue | 7 | en_US |
| dc.citation.spage | 1662 | en_US |
| dc.citation.volume | 52 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Su, P | en_US |
| dc.contributor.author | Lee, W | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:18:50Z | |
| dc.date.available | 2014-12-08T15:18:50Z | |
| dc.date.issued | 2005-07-01 | en_US |
| dc.description.abstract | This brief demonstrates that, through the perspective of body-source built-in potential lowering (Delta V-bi), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOS-FETs can be explained and predicted by the geometry dependence of threshold voltage (V-T). The correlation between Delta V-bi and V-T unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip. | en_US |
| dc.identifier.doi | 10.1109/TED.2005.850626 | en_US |
| dc.identifier.issn | 0018-9383 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TED.2005.850626 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/13552 | |
| dc.identifier.wosnumber | WOS:000230123100053 | |
| dc.language.iso | en_US | en_US |
| dc.subject | body source built-in potential lowering | en_US |
| dc.subject | floating-body effect | en_US |
| dc.subject | silicon-on-insulator (SOI) CMOS | en_US |
| dc.subject | threshold voltage | en_US |
| dc.subject | partially depleted (PD) | en_US |
| dc.subject | fully depleted (FID) | en_US |
| dc.title | On the prediction of geometry-dependent floating-body effect in SOI MOSFETs | en_US |
| dc.type | Article | en_US |