PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
| dc.citation.epage | 214 | en_US |
| dc.citation.issue | 2 | en_US |
| dc.citation.spage | 208 | en_US |
| dc.citation.volume | 53 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Yeh, Chih-Ting | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:29:54Z | |
| dc.date.available | 2014-12-08T15:29:54Z | |
| dc.date.issued | 2013-02-01 | en_US |
| dc.description.abstract | A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. (C) 2012 Elsevier Ltd. All rights reserved. | en_US |
| dc.identifier.doi | 10.1016/j.microrel.2012.09.016 | en_US |
| dc.identifier.issn | 0026-2714 | en_US |
| dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1016/j.microrel.2012.09.016 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/21445 | |
| dc.identifier.wosnumber | WOS:000315614600006 | |
| dc.language.iso | en_US | en_US |
| dc.title | PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit | en_US |
| dc.type | Article | en_US |