SSH and SHHGaInP/GaAs HBT divide-by-3 prescalers with true 50% duty cycle
| dc.citation.epage | 797 | en_US |
| dc.citation.issue | 14 | en_US |
| dc.citation.spage | 796 | en_US |
| dc.citation.volume | 42 | en_US |
| dc.citation.woscount | 2 | |
| dc.contributor.author | Tseng, S. C. | en_US |
| dc.contributor.author | Meng, C. C. | en_US |
| dc.contributor.author | Chen, W. Y. | en_US |
| dc.contributor.department | 電信工程研究所 | zh_TW |
| dc.contributor.department | Institute of Communications Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:16:12Z | |
| dc.date.available | 2014-12-08T15:16:12Z | |
| dc.date.issued | 2006-07-06 | en_US |
| dc.description.abstract | Two 50% duty cycle divide-by-3 prescalers - sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers - in the 2 pm GaInP/GaAs heterojunction bipolar transistor (HBT) technology are realised. Current switchable emitter couple logic D flip-flops are employed to form both prescalers. The proposed SHH prescaler functions up to 2.6 GHz while the SSH prescaler operates from DC to 1.75 GHz. The maximum operating frequency of the SHH prescaler is enhanced about 50% compared with that of the SSH prescaler owing to better signal synchronisation. | en_US |
| dc.identifier.doi | 10.1049/el:20060553 | en_US |
| dc.identifier.issn | 0013-5194 | en_US |
| dc.identifier.journal | ELECTRONICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1049/el:20060553 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/12035 | |
| dc.identifier.wosnumber | WOS:000239467500010 | |
| dc.language.iso | en_US | en_US |
| dc.title | SSH and SHHGaInP/GaAs HBT divide-by-3 prescalers with true 50% duty cycle | en_US |
| dc.type | Article | en_US |