Anomalous substrate current in polycrystalline silicon thin-film transistors

Abstract

In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated the first time. With typical T-gate pattered structure, an abnormal high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, substrate current generated from impact ionization effect is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreements were found through a wide range of gate bias and various drain bias, verifying the validity of this unified model.