標題: Anomalous substrate current in polycrystalline silicon thin-film transistors
作者: Zan, HW
Chen, SC
Wang, SH
Chang, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated the first time. With typical T-gate pattered structure, an abnormal high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, substrate current generated from impact ionization effect is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreements were found through a wide range of gate bias and various drain bias, verifying the validity of this unified model.
URI: http://hdl.handle.net/11536/18597
ISBN: 0-7803-7999-3
期刊: ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE
起始頁: 469
結束頁: 472
顯示於類別:會議論文