On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

Abstract

The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.