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Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

dc.citation.epage1324en_US
dc.citation.issue8en_US
dc.citation.spage1315en_US
dc.citation.volume51en_US
dc.citation.woscount5
dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorChu, Li-Weien_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.date.accessioned2014-12-08T15:28:43Z
dc.date.available2014-12-08T15:28:43Z
dc.date.issued2011-08-01en_US
dc.description.abstractThe configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle. (C) 2011 Elsevier Ltd. All rights reserved.en_US
dc.identifier.doi10.1016/j.microrel.2011.03.016en_US
dc.identifier.issn0026-2714en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2011.03.016en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/20782
dc.identifier.wosnumberWOS:000293106600006
dc.language.isoen_USen_US
dc.titleDesign and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS processen_US
dc.typeArticleen_US

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