極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(I)
| dc.contributor.author | 施敏 | en_US |
| dc.contributor.author | SZE SIMON MIN | en_US |
| dc.contributor.department | 交通大學電子工程系 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:34:20Z | |
| dc.date.available | 2014-12-13T10:34:20Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC91-2215-E009-044 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=784404&docId=150770 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/92658 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | 極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(I) | zh_TW |
| dc.title | Study on the Integration of Ultra Low k(k<2.2) and Copper Interconnect in ULSI Application (I) | en_US |
| dc.type | Plan | en_US |