Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation
| dc.citation.epage | 1243 | en_US |
| dc.citation.spage | 1240 | en_US |
| dc.contributor.author | Tsai, Hui-Wen | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:13:13Z | |
| dc.date.available | 2014-12-08T15:13:13Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | A new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application. | en_US |
| dc.identifier.doi | 10.1109/ICECS.2007.4511221 | en_US |
| dc.identifier.isbn | 978-1-4244-1377-5 | en_US |
| dc.identifier.journal | 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2007.4511221 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/10211 | |
| dc.identifier.wosnumber | WOS:000255014801130 | |
| dc.language.iso | en_US | en_US |
| dc.title | Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation | en_US |
| dc.type | Proceedings Paper | en_US |