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A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

dc.citation.epage295en_US
dc.citation.issue2en_US
dc.citation.spage283en_US
dc.citation.volume15en_US
dc.citation.woscount3
dc.contributor.authorLee, KBen_US
dc.contributor.authorLin, JYen_US
dc.contributor.authorJen, CWen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:35:06Z
dc.date.available2014-12-08T15:35:06Z
dc.date.issued2005-02-01en_US
dc.description.abstractMPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one, clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed;by the contexts, and it is capable of encoding either a singe symbol, or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-mum 1P4M CMOS technology, the design can run at 90 MHz.en_US
dc.identifier.doi10.1109/TCSVT.2004.841724en_US
dc.identifier.issn1051-8215en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGYen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSVT.2004.841724en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/23821
dc.identifier.wosnumberWOS:000226757300008
dc.language.isoen_USen_US
dc.subjectcontext-based arithmetic encodingen_US
dc.subjectMPEG-4en_US
dc.subjectshape codingen_US
dc.titleA multisymbol context-based arithmetic coding architecture for MPEG-4 shape codingen_US
dc.typeArticleen_US

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