SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
| dc.citation.epage | 68 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 58 | en_US |
| dc.citation.volume | 3 | en_US |
| dc.citation.woscount | 16 | |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Hsu, KC | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:40:21Z | |
| dc.date.available | 2014-12-08T15:40:21Z | |
| dc.date.issued | 2003-09-01 | en_US |
| dc.description.abstract | Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT_SCR) device has been confirmed to be significantly reduced by this double-triggered technique. | en_US |
| dc.identifier.doi | 10.1109/TDMR.2003.815192 | en_US |
| dc.identifier.issn | 1530-4388 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TDMR.2003.815192 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/27557 | |
| dc.identifier.wosnumber | WOS:000187434800001 | |
| dc.language.iso | en_US | en_US |
| dc.subject | double-triggered technique | en_US |
| dc.subject | electrostatic discharge (ESD) | en_US |
| dc.subject | ESD protection circuit | en_US |
| dc.subject | silicon-controlled rectifier (SCR) | en_US |
| dc.title | SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes | en_US |
| dc.type | Article | en_US |