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TRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFET

dc.citation.epage294en_US
dc.citation.issue2en_US
dc.citation.spage288en_US
dc.citation.volume42en_US
dc.citation.woscount7
dc.contributor.authorGUO, JCen_US
dc.contributor.authorCHANG, MCen_US
dc.contributor.authorLU, CYen_US
dc.contributor.authorHSU, CCHen_US
dc.contributor.authorCHUNG, SSSen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:03:33Z
dc.date.available2014-12-08T15:03:33Z
dc.date.issued1995-02-01en_US
dc.description.abstractFor the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5 x 10(16) similar to 5 x 10(17) cm(-3)), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics.en_US
dc.identifier.doi10.1109/16.370067en_US
dc.identifier.issn0018-9383en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.370067en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/2080
dc.identifier.wosnumberWOS:A1995QD76800013
dc.language.isoen_USen_US
dc.titleTRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFETen_US
dc.typeArticleen_US

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