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Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1-xGaxAs channel capping layer

dc.citation.epage0en_US
dc.citation.issue6en_US
dc.citation.spage0en_US
dc.citation.volume5en_US
dc.citation.woscount0en_US
dc.contributor.authorHuang, Cheng-Haoen_US
dc.contributor.authorLi, Yimingen_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2019-04-03T06:38:39Z
dc.date.available2019-04-03T06:38:39Z
dc.date.issued2015-06-01en_US
dc.description.abstractIn this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1-xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85 degrees is needed for the device with an averaged grain size of NiSi below 4x4 nm(2). (C) 2015 Author(s).en_US
dc.identifier.doi10.1063/1.4922190en_US
dc.identifier.issn2158-3226en_US
dc.identifier.journalAIP ADVANCESen_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.4922190en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/128080
dc.identifier.wosnumberWOS:000357608000007en_US
dc.language.isoen_USen_US
dc.titleSimulation study of 14-nm-gate III-V trigate field effect transistor devices with In1-xGaxAs channel capping layeren_US
dc.typeArticleen_US

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