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Hardware Architecture for High-Performance Regular Expression Matching

dc.citation.epage993en_US
dc.citation.issue7en_US
dc.citation.spage984en_US
dc.citation.volume58en_US
dc.citation.woscount4
dc.contributor.authorLee, Tsern-Hueien_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2014-12-08T15:09:16Z
dc.date.available2014-12-08T15:09:16Z
dc.date.issued2009-07-01en_US
dc.description.abstractThis paper presents a bitmap-based hardware architecture for the Glushkov nondeterministic finite automaton (G-NFA), which recognizes a given regular expression. We show that the inductions of the functions needed to construct the G-NFA can be generalized to include other special symbols commonly used in extended regular expressions such as the POSIX 1003.2 format. Our proposed implementation can detect the ending positions of all substrings of an input string T, which start at arbitrary positions of T and belong to the language defined by the given regular expression. To achieve high performance, the implementation is generalized to the NFA, which processes K symbols in each operation cycle. We provide an efficient solution for the boundary condition when the length of the input string is not an integral multiple of K. Compared with previous designs, our proposed architecture is more flexible and programmable because the pattern matching engine uses memory rather than logic.en_US
dc.identifier.doi10.1109/TC.2008.145en_US
dc.identifier.issn0018-9340en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TC.2008.145en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/7073
dc.identifier.wosnumberWOS:000266273200010
dc.language.isoen_USen_US
dc.subjectHardware accelerationen_US
dc.subjectnondeterministic finite automatonen_US
dc.subjectregular expressionen_US
dc.titleHardware Architecture for High-Performance Regular Expression Matchingen_US
dc.typeArticleen_US

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