CMOS power amplifier with ESD protection design merged in matching network

Abstract

A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-mu m CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.