A model for low-temperature operation of minority-carrier well-type guard rings in epitaxial CMOS structures
| dc.citation.epage | 457 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 453 | en_US |
| dc.citation.volume | 42 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Huang, CY | en_US |
| dc.contributor.author | Chen, MJ | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:49:17Z | |
| dc.date.available | 2014-12-08T15:49:17Z | |
| dc.date.issued | 1998-03-01 | en_US |
| dc.description.abstract | As temperature is lowered, behaviors of well-type guard rings in an epitaxial substrate are quite different from those at RT so that the previous formulation is unable to reflect these discrepancies precisely. This leads to a new escape-current model suitable for low-temperature applications. In addition to the structural parameters, the new model is also functions of other physical quantities such as temperature, high-level injection, surface recombination velocity at the high/low junction and minority-carrier transport parameters, which are also important at low temperature. (C) 1997 Elsevier Science Ltd. | en_US |
| dc.identifier.issn | 0038-1101 | en_US |
| dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/32773 | |
| dc.identifier.wosnumber | WOS:000073203900025 | |
| dc.language.iso | en_US | en_US |
| dc.title | A model for low-temperature operation of minority-carrier well-type guard rings in epitaxial CMOS structures | en_US |
| dc.type | Article | en_US |