A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC
| dc.citation.epage | 464 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 447 | en_US |
| dc.citation.volume | 17 | en_US |
| dc.citation.woscount | 2 | |
| dc.contributor.author | WU, CY | en_US |
| dc.contributor.author | LIN, YT | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:05:45Z | |
| dc.date.available | 2014-12-08T15:05:45Z | |
| dc.date.issued | 1989-10-01 | en_US |
| dc.identifier.issn | 0098-9886 | en_US |
| dc.identifier.journal | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/4292 | |
| dc.identifier.wosnumber | WOS:A1989AV69100006 | |
| dc.language.iso | en_US | en_US |
| dc.title | A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC | en_US |
| dc.type | Article | en_US |