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A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire

dc.citation.epage97en_US
dc.citation.issue1en_US
dc.citation.spage93en_US
dc.citation.volume3en_US
dc.citation.woscount12
dc.contributor.authorHu, SFen_US
dc.contributor.authorWu, YCen_US
dc.contributor.authorSung, CLen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:39:32Z
dc.date.available2014-12-08T15:39:32Z
dc.date.issued2004-03-01en_US
dc.description.abstractA dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.en_US
dc.identifier.doi10.1109/TNANO.2003.820784en_US
dc.identifier.issn1536-125Xen_US
dc.identifier.journalIEEE TRANSACTIONS ON NANOTECHNOLOGYen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TNANO.2003.820784en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/26986
dc.identifier.wosnumberWOS:000220457800016
dc.language.isoen_USen_US
dc.subjectnanotechnologyen_US
dc.subjectquantum dots (QD)en_US
dc.subjectquantum miresen_US
dc.subjectsilicon-on-insulator (SOI) technologyen_US
dc.titleA dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowireen_US
dc.typeArticleen_US

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