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Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications

dc.citation.epage783en_US
dc.citation.issue2en_US
dc.citation.spage781en_US
dc.citation.volume14en_US
dc.citation.woscount0
dc.contributor.authorChen, Shih-Hungen_US
dc.contributor.authorLinten, Dimitrien_US
dc.contributor.authorScholz, Mirkoen_US
dc.contributor.authorHuang, Yu-Chingen_US
dc.contributor.authorHellings, Geerten_US
dc.contributor.authorBoschke, Romanen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorGroeseneken, Guidoen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.date.accessioned2014-12-08T15:36:21Z
dc.date.available2014-12-08T15:36:21Z
dc.date.issued2014-06-01en_US
dc.description.abstractCDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.en_US
dc.identifier.doi10.1109/TDMR.2014.2320538en_US
dc.identifier.issn1530-4388en_US
dc.identifier.journalIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITYen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TDMR.2014.2320538en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/24689
dc.identifier.wosnumberWOS:000337132200029
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectcharged device model (CDM)en_US
dc.subjectcross-power domains ESD eventsen_US
dc.subject3D stacked ICsen_US
dc.subjectvary-fast transmission line pulsing (vfTLP) systemsen_US
dc.titleLocal CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applicationsen_US
dc.typeArticleen_US

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