Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography
| dc.citation.epage | en_US | |
| dc.citation.issue | 4 | en_US |
| dc.citation.volume | 53 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Lin, Cheng-I | en_US |
| dc.contributor.author | Lee, Ko-Hui | en_US |
| dc.contributor.author | Lin, Horng-Chih | en_US |
| dc.contributor.author | Huang, Tiao-Yuan | en_US |
| dc.contributor.department | 電機工程學系 | zh_TW |
| dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:36:25Z | |
| dc.date.available | 2014-12-08T15:36:25Z | |
| dc.date.issued | 2014-04-01 | en_US |
| dc.description.abstract | In this work, we have successfully demonstrated the feasibility of a method, which relies solely on I-line-based lithography, for fabricating sub-100nm tri-gated junctionless (JL) poly-Si nanowire (NW) transistors. This method employs sidewall spacer etching and photoresist (PR) trimming techniques to shrink the channel length and width, respectively. With this approach, channel length and width down to 90 and 93nm, respectively, are achieved in this work. The fabricated devices exhibit superior device characteristics with low subthreshold swing of 285mV/dec and on/off current ratio larger than 10(7). (C) 2014 The Japan Society of Applied Physics | en_US |
| dc.identifier.doi | 10.7567/JJAP.53.04EA01 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.7567/JJAP.53.04EA01 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/24748 | |
| dc.identifier.wosnumber | WOS:000338185100002 | |
| dc.language.iso | en_US | en_US |
| dc.title | Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography | en_US |
| dc.type | Article | en_US |