針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究(II)

dc.contributor.author	沈文仁	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
dc.date.accessioned	2014-12-13T10:37:18Z
dc.date.available	2014-12-13T10:37:18Z
dc.date.issued	1999	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.identifier.govdoc	NSC88-2215-E009-063	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=444886&docId=80597	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/94529
dc.language.iso	zh_TW	en_US
dc.subject	場可程式閘列	zh_TW
dc.subject	最佳化	zh_TW
dc.subject	合成	zh_TW
dc.subject	分割	zh_TW
dc.subject	電路集群	zh_TW
dc.subject	Field programmable gate array (FPGA)	en_US
dc.subject	Optimization	en_US
dc.subject	Synthesis	en_US
dc.subject	Partitioning	en_US
dc.subject	Circuit clustering	en_US
dc.title	針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究(II)	zh_TW
dc.title	A Study of Area/Performance Optimization and Partitioning for Field Programmable Gate Arrays (II)	en_US
dc.type	Plan	en_US

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