Fuzzy-based CMOS circuit partitioning in built-in current testing
| dc.citation.epage | 120 | en_US |
| dc.citation.issue | 1 | en_US |
| dc.citation.spage | 116 | en_US |
| dc.citation.volume | 7 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Tseng, WD | en_US |
| dc.contributor.author | Wang, KC | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:46:51Z | |
| dc.date.available | 2014-12-08T15:46:51Z | |
| dc.date.issued | 1999-03-01 | en_US |
| dc.description.abstract | We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties. | en_US |
| dc.identifier.doi | 10.1109/92.748207 | en_US |
| dc.identifier.issn | 1063-8210 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/92.748207 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/31495 | |
| dc.identifier.wosnumber | WOS:000078920900013 | |
| dc.language.iso | en_US | en_US |
| dc.subject | CMOS | en_US |
| dc.subject | cost | en_US |
| dc.subject | partitioning | en_US |
| dc.subject | performance | en_US |
| dc.subject | test | en_US |
| dc.title | Fuzzy-based CMOS circuit partitioning in built-in current testing | en_US |
| dc.type | Article | en_US |