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Design and Implementation of Sensorless Capacitor Voltage Balancing Control for Three-Level Boosting PFC

dc.citation.epage3817en_US
dc.citation.issue7en_US
dc.citation.spage3808en_US
dc.citation.volume29en_US
dc.citation.woscount1
dc.contributor.authorChen, Hung-Chien_US
dc.contributor.authorLiao, Jhen-Yuen_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.date.accessioned2014-12-08T15:34:54Z
dc.date.available2014-12-08T15:34:54Z
dc.date.issued2014-07-01en_US
dc.description.abstractCompared with the conventional boosting PFC converter, the three-level boosting PFC converter has two cascaded switches and two cascaded capacitors across the dc-side voltage. Two capacitor voltages may be different due to their mismatched equivalent series resistance, their mismatched capacitance, and the mismatched conducting time of the corresponding switches. It follows that the controller needs to sense the capacitor voltages to balance both capacitor voltages. In this paper, the sensorless capacitor voltage balancing control (SCVBC) without sensing the capacitor voltages is proposed, and the total number of the feedback signals is saved. The proposed SCVBC is digitally implemented in an FPGA-based system. The provided simulated and experimental results also demonstrate the proposed SCVBC.en_US
dc.identifier.doi10.1109/TPEL.2013.2279718en_US
dc.identifier.issn0885-8993en_US
dc.identifier.journalIEEE TRANSACTIONS ON POWER ELECTRONICSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TPEL.2013.2279718en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/23740
dc.identifier.wosnumberWOS:000332013100052
dc.language.isoen_USen_US
dc.subjectSensorless controlen_US
dc.subjectvoltage-balancing controlen_US
dc.titleDesign and Implementation of Sensorless Capacitor Voltage Balancing Control for Three-Level Boosting PFCen_US
dc.typeArticleen_US

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