SWITCHED-CAPACITOR PIPELINED LOGARITHMIC A/D AND D/A CONVERTERS
| dc.citation.epage | 716 | en_US |
| dc.citation.issue | 6 | en_US |
| dc.citation.spage | 714 | en_US |
| dc.citation.volume | 138 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | CHENG, MH | en_US |
| dc.contributor.author | HUANG, TC | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:05:05Z | |
| dc.date.available | 2014-12-08T15:05:05Z | |
| dc.date.issued | 1991-12-01 | en_US |
| dc.description.abstract | The paper presents two switched-capacitor circuits with modest complexity to implement a pipelined logarithmic digital-analogue convertor (LDAC) and logarithmic analogue-digital convertor (LADC), respectively, which spend only one clock time per conversion. In addition, the effect of the capacitor-ratio mismatch on the conversion errors of the convertor circuits is discussed. Hence, from the available maximum capacitor-ratio value and mismatch of the present integrated circuit (IC) technology, the feasible bit length of the pipelined LDAC and LADC can be computed. | en_US |
| dc.identifier.issn | 0956-3768 | en_US |
| dc.identifier.journal | IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3615 | |
| dc.identifier.wosnumber | WOS:A1991GT22800013 | |
| dc.language.iso | en_US | en_US |
| dc.subject | CONVERTERS | en_US |
| dc.subject | CIRCUIT THEORY AND DESIGN | en_US |
| dc.title | SWITCHED-CAPACITOR PIPELINED LOGARITHMIC A/D AND D/A CONVERTERS | en_US |
| dc.type | Article | en_US |