BIST for measuring clock jitter of charge-pump phase-locked loops
| dc.citation.epage | 285 | en_US |
| dc.citation.issue | 2 | en_US |
| dc.citation.spage | 276 | en_US |
| dc.citation.volume | 57 | en_US |
| dc.citation.woscount | 19 | |
| dc.contributor.author | Hsu, Jen-Chien | en_US |
| dc.contributor.author | Su, Chauchin | en_US |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:12:36Z | |
| dc.date.available | 2014-12-08T15:12:36Z | |
| dc.date.issued | 2008-02-01 | en_US |
| dc.description.abstract | This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%. | en_US |
| dc.identifier.doi | 10.1109/TIM.2007.910109 | en_US |
| dc.identifier.issn | 0018-9456 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TIM.2007.910109 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/9691 | |
| dc.identifier.wosnumber | WOS:000252338000009 | |
| dc.language.iso | en_US | en_US |
| dc.subject | analog built-in self-test (BIST) | en_US |
| dc.subject | jitter measurement | en_US |
| dc.subject | on-chip measurement | en_US |
| dc.subject | phase-locked loop (PLL) BIST | en_US |
| dc.subject | time-to-digital converter (TDC) | en_US |
| dc.title | BIST for measuring clock jitter of charge-pump phase-locked loops | en_US |
| dc.type | Article | en_US |