Investigation of analogue performance for process-induced-strained PMOSFETs
| dc.citation.epage | 407 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 404 | en_US |
| dc.citation.volume | 22 | en_US |
| dc.citation.woscount | 5 | |
| dc.contributor.author | Kuo, Jack J-Y | en_US |
| dc.contributor.author | Chen, William P-N | en_US |
| dc.contributor.author | Su, Pin | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:14:23Z | |
| dc.date.available | 2014-12-08T15:14:23Z | |
| dc.date.issued | 2007-04-01 | en_US |
| dc.description.abstract | This paper investigates the analogue performance of process-induced-strained PMOSFETs for system-on-a chip applications. Through a comparison between co-processed strained and unstrained PMOSFETs regarding important analogue metrics such as transconductance to drain current ratio (g(m)/I-d), output resistance, dc gain and the gain-bandwidth product, the impact of process-induced uniaxial strain on the analogue performance of MOS devices has been assessed and analysed. Our study may provide insights for analogue design using advanced strained devices. | en_US |
| dc.identifier.doi | 10.1088/0268-1242/22/4/019 | en_US |
| dc.identifier.issn | 0268-1242 | en_US |
| dc.identifier.journal | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1088/0268-1242/22/4/019 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/10978 | |
| dc.identifier.wosnumber | WOS:000246104100019 | |
| dc.language.iso | en_US | en_US |
| dc.title | Investigation of analogue performance for process-induced-strained PMOSFETs | en_US |
| dc.type | Article | en_US |